Most small computer systems today do not include floating point arithmetic in the CPU. Instead it is commonly done with software at great expense in speed. External arithmetic coprocessors have been developed to overcome this speed problem, but introduce new problems in their development.
The present invention is directed toward a barrel shifter for a floating point arithmetic unit that uses the IEEE format for representing floating numbers. It is a binary format, and as a result, a great deal of shifting is required in calculations. This is a time consuming process using a conventional shift register technique.
It is an object of the invention to enhance the performance of the shifting operations required for floating point calculations.
It is another object of the invention to allow for shifts of an arbitrary number of bits in either direction.
The shifting processes involved in floating point arithmetic are required in two instances. The first of these occurs when numbers are first brought into the floating point arithmetic unit. These numbers must be aligned so that the decimal (binary) points align. This process involves right shifting the smaller number and is referred to as denormalization.
The second instance occurs after the answer is calculated. The answer must be realigned into a standard format which usually involves left shifting. This process is called normalization.
The barrel shifter of the present invention is designed to handle both normalization and denormalization problems at high speed. It operates in two modes, shifting and normalization. In the shifting mode, a 6 bit binary shift code is provided externally, and the BSN (Barrel Shifter Normalizer) will shift the data that many places. The direction of the shift may also be controlled. Conventional barrel shifters require a large number of gates to implement both left and right shifts. This is because the shifting stages are in essence duplicated. In contrast, the present invention allows the barrel shifter to only shift left. A bit reverser is placed before the barrel shifter and a bit reverser is placed after the output of the barrel shifter. As can be seen, bit reversing a number, shifting it left, and then bit reversing the output is the same as right shifting a number.
It is an object of the present invention to minimize the number of gates required to implement both left and right shifting.
In normalization mode, the barrel shifter/normalizer (BSN) automatically shifts the data until a 1 is in a predefined and fixed location in the data. In other words, leading zeros are automatically shifted out. A separate 6 bit output indicates how far the shift was. Simple barrel shifters have existed for a long time but they have not had the normalization capability.
It is therefore an object of the invention to allow automatic normalization with an output indicating the number of bits shifted.
This and other objects of the invention are achieved by a barrel shifter comprising:
a first bit reverser stage having a first input for a first plurality of data bits and a first output bus for a second plurality of data bits;
said first bit reverser stage selectively, in response to a first control signal, causing said first plurality of data bits to appear on said first output bus as said second plurality of data bits and reversing the order of said second plurality of data bits:
a shifting stage having a second input coupled to said first output bus for receiving said second plurality of data bits, and a second output bus for a third plurality of data bits;
said shifting stage selectively, in response to a second control signal, causing said second plurality of data bits to be shifted in a first direction and output as said third plurality of data bits on said second output bus;
a second bit reverser stage having a third input coupled to said second output bus for said third plurality of data bits, and a third output bus for a fourth plurality of data bits; and
said second bit reverser stage selectively, in response to a third control signal, causing said third plurality of data bits to appear on said third output bus as said fourth plurality of data bits and reversing the order of said fourth plurality of data bits.